1. Field of the Invention
This invention relates to a video data processing circuit for use with an image display unit such as a CRT display unit for displaying an image on the image display unit in accordance with video data stored in a video memory (or a refresh buffer).
2. Prior Art
In an ordinary image display system, display of image is effected on a CRT display screen based on video data sequentially read from a video memory. And therefore, to enhance the resolution of displayed images, such image display system requires a video memory of a large storage capacity and video data must be read therefrom at a higher speed or rate. When it is required to effect color display of the image, the storage capacity of the video memory and the speed of reading of the data from the video memory must be further increased. On the other hand, to increase the number of colors used in the color display, the amount of video data must also be increased, and therefore a video data processing circuit capable of reading the video data from the video memory at a very high speed is necessary.
FIG. 1 shows one conventional data processing circuit for an image display system which is so designed as to read video data from a video memory at a high speed. This video data processing circuit is so arranged that an image composed of 1024.times.800 pixels (or dots) is displayed on a CRT display screen by a non-interlaced scanning at a frequency of 60 Hz, the time required to display one pixel being 15.7 nsec.
In FIG. 1, shown at 1 to 4 are video RAMs (hereinafter referred to as "VRAM") each comprising sixteen RAM chips of 64K address by one bit organization. More specifically, the VRAM 1 comprises RAMs 1.sub.1 to 1.sub.16, the VRAM 2 comprises RAMs 2.sub.1 to 2.sub.16, the VRAM 3 comprises RAMs 3.sub.1 to 3.sub.16, and the VRAM 4 comprises RAMs 4.sub.1 to 4.sub.16. Each of the RAMs are assigned the same addresses, so that a 16-bit data is readout from each of the VRAMs 1 to 4 by one access thereto.
The four groups of 16-bit data read from the VRAMs 1 to 4 are supplied in parallel to parallel-to-serial converters (P/S converter) 5 to 8, respectively. Each of the P/S converters 5 to 8 converts the supplied 16-bit data into a serial data, and supplies the serial data bit by bit at a time interval of 15.7 nsec to a look-up table 10, the bits outputted simultaneously from the P/S converters 5 to 8 form 4-bit video data for one pixel. The look-up table 10 comprises a RAM (not shown) and converts each of the 4-bit data (video data) supplied from the P/S converters 5 to 8 into color data composed of red, green and blue data based on conversion data stored in the RAM. The conversion data provided in the look-up table 10 can be changed by a central processing unit (CPU) 11. The look-up table 10 performs the conversion operation (or the readout operation) at a time interval of 15.7 nsec. The number of bits (n) of the color data outputted from the look-up table 10 is generally greater than the number of bits (m) of the video data inputted thereto, and therefore the look-up table 10 can be arranged so that one of 2.sup.m colors is selected from 2.sup.n colors. In the case of the system of FIG. 1, "m" is equal to four, and therefore, one of sixteen colors can be selected from 2.sup.n colors. Thus, the number of selectable colors can be increased by augmenting the number of VRAMs.
The color data outputted from the look-up table 10 is supplied to a digital-to-analog converter (DAC) 12 which converts the red, green and blue data contained in each color data into analog red, green and blue signals R, G and B, respectively. These analog signals R, G and B are supplied to a CRT display unit 13, whereby a color image is displayed on a screen thereof.
In the above-described conventional system, the shift operation effected by the P/S converters 5 to 8 and the readout operation effected in the look-up table 10 must be synchronized with the display operation or scanning of the CRT display unit 13. More specifically, the shift operation of the P/S converters 5 to 8 and the readout operation of the look-up table 10 must be effected at a time interval of 15.7 nsec which corresponds to a time period required to display one pixel on the screen of the CRT display unit 13 (i.e., a dot display period). Thus, to enhance the resolution of images displayed on the CRT display unit 13, the speed of operation of the P/S converters 5 to 8 and the look-up table 10 must be increased quite a lot, which is, however, is very difficult.